Memory controllers are used in data processing systems to interface between different types of memory and one or more data processing masters. The various types of memory include SRAM, DRAM, Flash, ROM, MRAM and others. High performance data processor systems use ‘smart’ memory controllers that reduce read and write memory latency, thereby helping the data processor to continue execution of the instruction stream. A memory controller does not conventionally utilize a prefetch buffer for fetching required data in advance of when the data is needed by the processor. A ‘smart’ memory controller however incorporates a prefetch buffer for the purpose of obtaining data in advance of when the data is requested by the data processor. The prefetching unit of a smart memory controller includes Tag, Data and Status storage locations that are used to identify and supply the data to the data processor.
A method in U.S. Pat. No. 6,529,998 entitled “Adaptive Prefetching Of Data From A Disk” has been proposed for adaptively selecting an optimal prefetch policy for prefetching data from a disk storage. A policy is used that is based on a past history of read and write misses. A threshold value is used along with a random number to determine the prefetch policy. The threshold value is defined and updated based upon the number of avoidable read misses that occur during operation. The system predetermines a static fixed size buffer and is therefore limited for use in systems having multiple bus masters and various memories.
A method in U.S. Pat. No. 5,958,040 entitled “Adaptive Stream Buffers” uses instruction-specific prefetching avoidance. A table stores address information on which cache lines are not used each time a CPU executes an instruction. Subsequent instruction addresses are compared to the addresses in the table, and a buffer is not allocated when a subsequent address is found within the table. This system is limited to operation on an instruction stream (instruction read operations) and does not respond to data read accesses. Therefore data read accesses are not optimized for performance, and the disclosed system is limited to a fixed size buffer.
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